Computers are known to include processors, memory, and display devices. Advancements in computer technology have enabled computers to be used in more and more applications where diverse displaying options are desirable. Video graphics circuits that are able to provide these diverse displaying options need to be able to do so in a cost efficient manner without consuming large amounts of processor and memory resources.
Video graphics circuits store information relating to the display, or video graphics data, in memories. Video graphics data stored in memory must be stored in such a manner that it can be stored and retrieved quickly enough for the graphics processor to update and display the image rapidly and efficiently. For this reason, video graphics data is often mapped to the memory in a linear or tiled fashion. Data that is linearly mapped in memory has sequential pixels of a single row stored sequentially in the memory. Tile mapping breaks the display into blocks or tiles such that sequential pixels within each block are stored sequentially, thus localizing the storage of individual blocks rather than entire rows.
In order to accommodate multiple displays, multiple graphics processors using multiple memories are often required. These multiple processors may require many different amounts of memory based on the displaying parameters selected. For this reason, processors often require the flexibility to change the amount of memory they are allocated for storage of video graphics data. For example, a display may increase its resolution, thus requiring additional memory to store the information relating to the added resolution. In such systems, large blocks of memory may have to be added or subtracted from the portion of memory allocated to a particular graphics processor. In such instances, memory-mapping techniques such as virtual addressing are ineffective, as they cannot meet the speed and efficiency requirements of video graphics processors. Therefore, the block of memory allocated to a video graphics processor for storage of video graphics data should be a contiguous block of memory. This is necessary to satisfy the sequential mapping constraints of linear and tile mapping techniques. In multiple processor systems where each processor has a corresponding memory, each of the multiple memories must be of such a size as to accommodate the maximum memory requirements for its corresponding processor, even though all of the memory may only be used occasionally.
In other words, a processor may have to have a 4-Megabyte memory for video graphics data even though it only uses 1 Megabyte in normal operation. The additional 3 Megabytes may only be required for occasional large-matrix, high-resolution operations, and therefore left idle the majority of the time.
Therefore, a need exists for a memory allocation technique that reduces the amount of memory required when multiple processors are used, where the allocation technique allows the size of memory allocated to a particular processor to change while still allowing for linear or tile mapping of the graphics data.